TABLE OF CONTENTS
Overview External Ports Processor    my_microblaze           memory map Debuggers    debug_module Busses    lmb_data    lmb_instr    opb_peripherals Memory    bram_mem Memory Controllers    lmb_cntlr_data    lmb_cntlr_instr Peripherals    my_gpio    my_timer    my_uart Timing Information

Overview TOC Overview Generated on Wed May 31 12:55:26 2006 Source D:/Curso_MBlaze_PPC/H3PB_Simple/system.xmp EDK Version 8.1.01 FPGA Family spartan3 Device xc3s400ft256-5 # IP Instantiated 11 # Processors 1 # Busses 3

Block Diagram TOC

External Ports TOC EXTERNAL PORTS These are the external ports defined in the MHS file. Attributes Key CLK  are clock ports  INTR  are interrupt ports  BUF or REG  are ports that instantiate or infer IOB primitives:  # NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB sys_clk I 1 sys_clk  CLK  1GLB sys_rst I 1 sys_rst 2A leds IO 0:5 leds

Processors TOC my_microblaze   MicroBlaze The MicroBlaze 32 bit soft processor PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL Bus Interfaces MASTERSHIP NAME STD BUS P2P MASTER DOPB OPB opb_peripherals NA MASTER IOPB OPB opb_peripherals NA MASTER DLMB LMB lmb_data lmb_cntlr_data MASTER ILMB LMB lmb_instr lmb_cntlr_instr General IP Core microblaze Version 4.00.a Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_ADDR_TAG_BITS 0 C_ALLOW_DCACHE_WR 1 C_ALLOW_ICACHE_WR 1 C_CACHE_BYTE_SIZE 8192 C_DCACHE_ADDR_TAG 0 C_DCACHE_BASEADDR 0x00000000 C_DCACHE_BYTE_SIZE 8192 C_DCACHE_HIGHADDR 0x3FFFFFFF C_DCACHE_USE_FSL 0 C_DEBUG_ENABLED 1 C_DIV_ZERO_EXCEPTION 0 C_DOPB_BUS_EXCEPTION 0 C_D_LMB 1 C_D_OPB 1 C_EDGE_IS_POSITIVE 1 C_FAMILY spartan3 C_FPU_EXCEPTION 0 C_FSL_DATA_SIZE 32 C_FSL_LINKS 0 C_ICACHE_BASEADDR 0x00000000 Name Value C_ICACHE_HIGHADDR 0x3FFFFFFF C_ICACHE_USE_FSL 0 C_ILL_OPCODE_EXCEPTION 0 C_INSTANCE my_microblaze C_INTERRUPT_IS_EDGE 0 C_IOPB_BUS_EXCEPTION 0 C_I_LMB 1 C_I_OPB 1 C_NUMBER_OF_PC_BRK 2 C_NUMBER_OF_RD_ADDR_BRK 1 C_NUMBER_OF_WR_ADDR_BRK 1 C_UNALIGNED_EXCEPTIONS 0 C_USE_BARREL 0 C_USE_DCACHE 0 C_USE_DIV 0 C_USE_FPU 0 C_USE_HW_MUL 1 C_USE_ICACHE 0 C_USE_MSR_INSTR 0 C_USE_PCMP_INSTR 0 MEMORY MAP D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE D I BASE HIGH MODULE ■   0x00000000 0x00001FFF lmb_cntlr_data   ■ 0x00000000 0x00001FFF lmb_cntlr_instr ■ ■ 0xFFFF0000 0xFFFF00FF my_gpio ■ ■ 0xFFFF1000 0xFFFF10FF my_uart ■ ■ 0xFFFF2000 0xFFFF20FF debug_module ■ ■ 0xFFFF3000 0xFFFF30FF my_timer Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Debuggers TOC debug_module   OPB Microprocessor Debug Module (MDM) MicroBlaze Debug Module with OPB interface PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL Bus Interfaces MASTERSHIP NAME STD BUS P2P SLAVE SOPB OPB opb_peripherals NA General IP Core opb_mdm Version 2.00.a Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0xFFFF2000 C_FAMILY spartan3 C_HIGHADDR 0xFFFF20FF C_MB_DBG_PORTS 1 C_OPB_AWIDTH 32 C_OPB_DWIDTH 32 C_UART_WIDTH 32 C_USE_UART 1 C_WRITE_FSL_PORTS 0 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Busses TOC lmb_data   Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 1 LMB_Clk I 1 sys_clk 2 SYS_Rst I 1 sys_rst Bus Connections TYPE NAME BIF MASTER my_microblaze DLMB SLAVE lmb_cntlr_data SLMB General IP Core lmb_v10 Version 1.00.a Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_EXT_RESET_HIGH 1 C_LMB_AWIDTH 32 C_LMB_DWIDTH 32 C_LMB_NUM_SLAVES 4 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. lmb_instr   Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 1 LMB_Clk I 1 sys_clk 2 SYS_Rst I 1 sys_rst Bus Connections TYPE NAME BIF MASTER my_microblaze ILMB SLAVE lmb_cntlr_instr SLMB General IP Core lmb_v10 Version 1.00.a Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_EXT_RESET_HIGH 1 C_LMB_AWIDTH 32 C_LMB_DWIDTH 32 C_LMB_NUM_SLAVES 4 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. opb_peripherals   On-chip Peripheral Bus (OPB) 2.0 OPB_V20 On-Chip Peripheral Bus V2.0 with OPB Arbiter (OPB_V20) PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 1 OPB_Clk I 1 sys_clk 2 SYS_Rst I 1 sys_rst Bus Connections TYPE NAME BIF MASTER my_microblaze DOPB MASTER my_microblaze IOPB SLAVE my_gpio SOPB SLAVE my_uart SOPB SLAVE debug_module SOPB SLAVE my_timer SOPB General IP Core opb_v20 Version 1.10.c Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0xFFFFFFFF C_DEV_BLK_ID 0 C_DEV_MIR_ENABLE 0 C_DYNAM_PRIORITY 0 C_EXT_RESET_HIGH 1 C_HIGHADDR 0x00000000 C_NUM_MASTERS 4 Name Value C_NUM_SLAVES 4 C_OPB_AWIDTH 32 C_OPB_DWIDTH 32 C_PARK 0 C_PROC_INTRFCE 0 C_REG_GRANTS 1 C_USE_LUT_OR 1 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Memory TOC bram_mem   Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL Bus Interfaces MASTERSHIP NAME STD BUS P2P TARGET PORTA XIL lmb_cntlr_data_BRAM_PORT lmb_cntlr_data TARGET PORTB XIL lmb_cntlr_instr_BRAM_PORT lmb_cntlr_instr General IP Core bram_block Version 1.00.a Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_FAMILY spartan3 C_MEMSIZE 2048 C_NUM_WE 4 C_PORT_AWIDTH 32 C_PORT_DWIDTH 32 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Memory Controllers TOC lmb_cntlr_data   LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL Bus Interfaces MASTERSHIP NAME STD BUS P2P INITIATOR BRAM_PORT XIL lmb_cntlr_data_BRAM_PORT bram_mem SLAVE SLMB LMB lmb_data my_microblaze General IP Core lmb_bram_if_cntlr Version 1.00.b Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0x00000000 C_HIGHADDR 0x00001fff C_LMB_AWIDTH 32 C_LMB_DWIDTH 32 C_MASK 0x00800000 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. lmb_cntlr_instr   LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL Bus Interfaces MASTERSHIP NAME STD BUS P2P INITIATOR BRAM_PORT XIL lmb_cntlr_instr_BRAM_PORT bram_mem SLAVE SLMB LMB lmb_instr my_microblaze General IP Core lmb_bram_if_cntlr Version 1.00.b Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0x00000000 C_HIGHADDR 0x00001fff C_LMB_AWIDTH 32 C_LMB_DWIDTH 32 C_MASK 0x00800000 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Peripherals TOC my_gpio   OPB General Purpose IO General Purpose Input/Output (GPIO) core for the On-Chip Peripheral Bus (OPB) bus. PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 1 GPIO_IO IO 0:5 leds Bus Interfaces MASTERSHIP NAME STD BUS P2P SLAVE SOPB OPB opb_peripherals NA General IP Core opb_gpio Version 3.01.b Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_ALL_INPUTS 0 C_ALL_INPUTS_2 0 C_BASEADDR 0xFFFF0000 C_DOUT_DEFAULT 0x00000000 C_DOUT_DEFAULT_2 0x00000000 C_FAMILY spartan3 C_GPIO_WIDTH 6 C_HIGHADDR 0xFFFF00FF C_INTERRUPT_PRESENT 0 Name Value C_IS_BIDIR 1 C_IS_BIDIR_2 1 C_IS_DUAL 0 C_OPB_AWIDTH 32 C_OPB_DWIDTH 32 C_TRI_DEFAULT 0xffffffff C_TRI_DEFAULT_2 0xffffffff C_USER_ID_CODE 3   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. my_timer   OPB Timer/Counter Timer counter with OPB interface PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL Bus Interfaces MASTERSHIP NAME STD BUS P2P SLAVE SOPB OPB opb_peripherals NA General IP Core opb_timer Version 1.00.b Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0xFFFF3000 C_COUNT_WIDTH 32 C_FAMILY spartan3 C_GEN0_ASSERT 1 C_GEN1_ASSERT 1 C_HIGHADDR 0xFFFF30FF Name Value C_ONE_TIMER_ONLY 0 C_OPB_AWIDTH 32 C_OPB_DWIDTH 32 C_TRIG0_ASSERT 1 C_TRIG1_ASSERT 1   Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information. my_uart   OPB UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for OPB bus. PORT LIST The ports listed here are only those connected in the MHS file. Refer to the IP documentation for complete information about module ports. # NAME DIR [LSB:MSB] SIGNAL 1 RX I 1 rx 2 TX O 1 tx Bus Interfaces MASTERSHIP NAME STD BUS P2P SLAVE SOPB OPB opb_peripherals NA General IP Core opb_uartlite Version 1.00.b Driver API Parameters These are parameters set for this module. Refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system. Name Value C_BASEADDR 0xFFFF1000 C_BAUDRATE 9600 C_CLK_FREQ 125 C_DATA_BITS 8 C_HIGHADDR 0xFFFF10FF C_ODD_PARITY 1 C_OPB_AWIDTH 32 C_OPB_DWIDTH 32 C_USE_PARITY 0 Post Synthesis Device Utilization Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Timing Information TOC Post Synthesis Clock Limits No clocks could be identified in the design. Run platgen to generate synthesis information.

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