m255
13
cModel Technology
dD:\Ivan\Curso_MBlaze_PPC\H3PB_Futaba\pcores\opb_futaba_v1_00_a\devl\projnav
Eipif_control_wr
w1136615145
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FC:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd
l0
L101
VZJJO>hb<M<f1X=WD9o;SL2
OE;C;6.1a;31
31
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Aimplementation
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work ipif_control_wr ZJJO>hb<M<f1X=WD9o;SL2
l279
L176
VLMH9>iF5ZATS><[_:ZBeb2
OE;C;6.1a;31
31
M2 ieee std_logic_1164
M1 ieee std_logic_arith
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Epf_dly1_mux
w1136615145
DP unisim vcomponents E@khmZNEKNNC5CFLMn=;N1
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DE proc_common_v2_00_a inferred_lut4 534@o1G`0j0P@n9=CjI`S0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FC:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd
l0
L107
VkXeo?[Ukne755bzK7LnX^1
OE;C;6.1a;31
31
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Aimplementation
DE proc_common_v2_00_a inferred_lut4 534@o1G`0j0P@n9=CjI`S0
DP unisim vcomponents E@khmZNEKNNC5CFLMn=;N1
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work pf_dly1_mux kXeo?[Ukne755bzK7LnX^1
l173
L125
V>X<DIBRG8^?Fm4A1`Yf802
OE;C;6.1a;31
31
M4 ieee std_logic_1164
M3 ieee std_logic_arith
M2 ieee std_logic_unsigned
M1 unisim vcomponents
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Ewrpfifo_dp_cntl
w1136615145
DE proc_common_v2_00_a pf_adder ZnCRLV;=UnzFmYXz:fXae0
DE proc_common_v2_00_a pf_occ_counter_top >nYfjn6QOES258=b6jchO1
DP unisim vcomponents E@khmZNEKNNC5CFLMn=;N1
DE proc_common_v2_00_a pf_counter_top TEIPRNL8CKeDC@[9>0oh@2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FC:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd
l0
L145
V`dn_K;AKUMY;CzPoV2j7D0
OE;C;6.1a;31
31
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Aimplementation
DE proc_common_v2_00_a pf_adder ZnCRLV;=UnzFmYXz:fXae0
DE proc_common_v2_00_a pf_occ_counter_top >nYfjn6QOES258=b6jchO1
DE proc_common_v2_00_a pf_counter_top TEIPRNL8CKeDC@[9>0oh@2
DP unisim vcomponents E@khmZNEKNNC5CFLMn=;N1
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wrpfifo_dp_cntl `dn_K;AKUMY;CzPoV2j7D0
l289
L189
V9:ka4TWR:I@Fh0TDG1hJ]3
OE;C;6.1a;31
31
M4 ieee std_logic_1164
M3 ieee std_logic_arith
M2 ieee std_logic_unsigned
M1 unisim vcomponents
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Ewrpfifo_top
w1136615146
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP unisim vcomponents E@khmZNEKNNC5CFLMn=;N1
DE proc_common_v2_00_a srl16_fifo >^hOem_zQYPV^c^aIS6;O3
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DE proc_common_v2_00_a pf_dpram_select C4i`VcCgKjVF2]dJ86bfk0
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FC:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd
l0
L178
VXTd5nXzGPWaZQI=^?<fV;3
OE;C;6.1a;31
31
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
Aimplementation
DE proc_common_v2_00_a srl16_fifo >^hOem_zQYPV^c^aIS6;O3
DE proc_common_v2_00_a pf_dpram_select C4i`VcCgKjVF2]dJ86bfk0
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP unisim vcomponents E@khmZNEKNNC5CFLMn=;N1
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wrpfifo_top XTd5nXzGPWaZQI=^?<fV;3
l424
L257
VQ]M:Dh;l7:U9hOMmC5S3@1
OE;C;6.1a;31
31
M5 ieee std_logic_1164
M4 ieee std_logic_arith
M3 ieee numeric_std
M2 unisim vcomponents
M1 ieee std_logic_unsigned
o-explicit -93 -work wrpfifo_v1_01_b
tExplicit 1 GenerateLoopIterationMax 100000
